基于FPGA的边沿检测-基础篇

边沿检测的设计绘制模块框图及波形图编写模块代码module rise_fall( input wire clk , input wire rst_n , input wire A , output reg A_rise , output reg A_fall ); reg A_r1; reg A_r2; reg A_r3; //多级打拍处理,消除亚稳态 //A_r1:稳定在70%~80%的输入信号 always(posedge clk or negedge rst_n) begin if(!rst_n) A_r1 1b0; else A_r1 A; end //A_r2:稳定在99%的输入信号 always(posedge clk or negedge rst_n) begin if(!rst_n) A_r2 1b0; else A_r2 A_r1; end //A_r3:A_r2打一拍 always(posedge clk or negedge rst_n) begin if(!rst_n) A_r3 1b0; else A_r3 A_r2; end //A_rise:采集上升沿 always(posedge clk or negedge rst_n) begin if(!rst_n) A_rise 1b0; else if(A_r3 1b0 A_r2 1b1)//~A_r3 A_r2 A_rise 1b1; else A_rise 1b0; end // always(posedge clk or negedge rst_n) // begin // if(!rst_n) // A_rise 1b0; // else // A_rise ~A_r3 A_r2; // end //A_fall:采集下降沿 always(posedge clk or negedge rst_n) begin if(!rst_n) A_fall 1b0; else if(A_r3 1b1 A_r2 1b0) A_fall 1b1; else A_fall 1b0; end endmodule编写仿真代码timescale 1ns/1ps module rise_fall_tb(); reg clk ; reg rst_n ; reg A ; wire A_rise ; wire A_fall ; initial begin clk 1b0; rst_n 1b0; A 1b0; #123 rst_n 1b1; end always #10 clk ~clk; always #333.33 A {$random} % 2; rise_fall rise_fall_inst( .clk (clk ) , .rst_n (rst_n ) , .A (A ) , .A_rise (A_rise) , .A_fall (A_fall) ); endmodule仿真验证仿真波形与绘制波形图一致仿真验证通过。